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CH7003B
CHRONTEL
Digital PC to TV Encoder
Features
* Input data path handles 8, 12, or 16-bit words in multiplexed or non-multiplexed form * Decodes pixel data in YCrCb (CCIR601 or 656) or RGB (15, 16 or 24-bit) formats * Supports 640x480, 640x400, 720x400, 800x600 and 512x384 input resolutions * Adjustable underscan for most modes * High quality 4-line flicker filtering * High resolution on-chip PLL * Fully programmable through I2C port * Supports NTSC, NTSC-EIA (Japan), and PAL (B, D, G, H, I, M and N) TV formats * Provides Composite, S-Video and SCART outputs * CCIR624-3 compliant (see exceptions) * Auto-detection of TV presence * Sub-carrier genlock and dot crawl control * Programmable power management * 9-bit video DAC outputs * Complete Windows and DOS driver software * Offered in a 44-pin PLCC, 44-pin TQFP
General Description
Chrontel's CH7003 digital PC to TV encoder is a standalone integrated circuit which provides a PC 99 compliant solution for TV output. It provides a universal digital input port to accept a pixel data stream from a compatible VGA controller (or equivalent) and converts this directly into NTSC or PAL TV format, with simultaneous composite and S-Video outputs. This circuit integrates a digital NTSC/PAL encoder with 9bit DAC interface, and new adaptive flicker filter, and high accuracy low-jitter phase locked loop to create outstanding quality video. Through its TrueScaleTM scaling and deflickering engine, the CH7003 supports full vertical and horizontal underscan capability and operates in 5 different resolutions including 640x480 and 800x600. A new universal digital interface along with full programmability make the CH7003 ideal for system-level PC solutions. All features are software programmable through a standard I2C port, to enable a complete PC solution using a TV as the primary display.
Patent number 5,781,241 Patent number 5,914,753
LINE MEMORY YUV-RGB CONVERTER
RGB-YUV CONVERTER DIGITAL
D[15:0 ] PIXEL DATA
INPUT INTERFACE
TRUE SCALE SCALING & DEFLICKERING ENGINE
NTSC/PAL ENCODER & FILTERS
Y/R
TRIPLE DAC
C/G CVBS/G
SYSTEM CLOCK
RSET
I 2C REGISTER & CONTROL BLOCK
PLL
TIMING & SYNC GENERATOR
SC
SD
ADDR
XCLK
H
V
XI XO/FIN CSYNC P-OUT BCO
Figure 1: Functional Block Diagram
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CHRONTEL
CH7003B
P-OUT
DGND
6
5
4
3
2
1
44
43
42
41
D[3] D[4] D[5] D[6] DVDD D[7] D[8] DGND] D[9] D[10] D[11]
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
40 39 38 37 36
AGND
DVDD
XCLK
BCO
D[2]
D[1]
D[0]
H
V
XO/FIN XI AVDD DVDD ADDR DGND SC SD VDD RSET GND
CHRONTEL CH7003
35 34 33 32 31 30 29
DVDD
CSYNC
DGND
GND
CVBS
C
D[12]
D[13]
D[14]
Figure 2: 44-pin PLCC
2
D[15]
Y
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Figure 3: 44-pin TQFP
CH7003B
P-OUT
DGND
44
43
42
41
40
39
38
37
36
35
D[3] D[4] D[5] D[6] DVDD D[7] D[8] DGND] D[9] D[10] D[11]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
34 33 32 31 30
AGND
DVDD
XCLK
BCO
D[2]
D[1]
D[0]
H
V
XO/FIN XI AVDD DVDD ADDR DGND SC SD VDD RSET GND
CHRONTEL CH7003
29 28 27 26 25 24 23
DVDD
CSYNC
DGND
GND
CVBS
C
D[12]
D[13]
D[14]
Figure 3: 44-PIN TQFP
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D[15]
Y
3
CHRONTEL
Table 1. Pin Description
44-Pin PLLC
21-15, 13-12, 10-4
CH7003B
Type
In
44-Pin TQFP
15,14, 13,12, 11,10, 9,7,6,4, 3,2, 1,44,43, 42 37
Symbol
D15-D0
Description
Digital Pixel Inputs These pins accept digital pixel data streams with either 8, 12, or 16-bit multiplexed or 16-bit non-multiplexed formats, determined by the input mode setting (see Registers and Programming section). Inputs D0 - D7 are used when operating in 8-bit multiplexed mode. Inputs D0 - D11 are used when operating in 12-bit mode. Inputs D0 - D15 are used when operating in 16-bit mode. The data structure and timing sequence for each mode is described in the section on Digital Video Interface. Pixel Clock Output The CH7003, operating in master mode, provides a pixel data clocking signal to the VGA controller. This pin provides the pixel clock output signal (adjustable as 1X, 2X or 3X) to the VGA controller (see the section on Digital Video Interface and Registers and Programming for more details). The capacitive loading on this pin should be kept to a minimum. Pixel Clock Input To operate in a pure master mode, the P-OUT signal should be connected to the XCLK input pin. To operate in a pseudo-master mode, the P-OUT clock is used as a reference frequency, and a signal locked to this output (at 1X, 1/2X, or 1/3X the P-OUT frequency) is input to the XCLK pin. To operate in slave mode, the CH7003 accepts an external pixel clock input at this pin. The capacitive loading on this pin should be kept to a minimum. Vertical Sync Input/Output This pin accepts the vertical sync signal from the VGA controller, or outputs a vertical sync to the VGA controller. The capacitive loading on this pin should kept to a minimum. Horizontal Sync Input/Output This pin accepts the horizontal sync from the VGA controller, or outputs a horizontal sync to the VGA controller. The capacitive loading on this pin should be kept to a minimum. Buffered Clock Output This pin provides a buffered output of the 14.31818 MHz crystal input frequency for other devices and remains active at all times (including power-down). The output can also be selected to be other frequencies (see Registers and Programming). Crystal Input A parallel resonance 14.31818 MHz ( 50 ppm) crystal should be attached between XI and XO/FIN. However, if an external CMOS clock is attached to XO/FIN, XI should be connected to ground. Crystal Output or External Fref A 14.31818 MHz ( 50 ppm) crystal may be attached between XO/FIN and XI. An external CMOS compatible clock can be connected to XO/FIN as an alternative. Reference Resistor A 360 resistor with short and wide traces should be attached between RSET and ground. No other connections should be made to this pin. Luminance Output A 75 termination resistor with short traces should be attached between Y and ground for optimum performance. In normal operating modes other than SCART, this pin outputs the luma video signal. In SCART mode, this pin outputs the red signal. Chrominance Output A 75 termination resistor with short traces should be attached between C and ground for optimum performance. In normal operating modes other than SCART, this pin outputs the chroma video signal. In SCART mode, this pin outputs the green signal.
43
Out
P-OUT
1
39
In
XCLK
3
41
In/Out
V
2
40
In/Out
H
41
35
Out
BCO
38
32
In
XI
39
33
In
XO/FIN
30
24
In
RSET
28
22
Out
Y/R
27
21
Out
C/G
4
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Table 1. Pin Description (continued)
44-Pin PLLC
26
CH7003B
Type
Out
44-Pin TQFP
20
Symbol
CVBS/B
Description
Composite Video Output A 75 termination resistor with short traces should be attached between CVBS and ground for optimum performance. In normal operating modes other than SCART, this pin outputs the composite video signal. In SCART mode, this pin outputs the blue signal. Composite Sync Output A 75 termination resistor with short traces should be attached between CSYNC and ground for optimum performance. In SCART mode, this pin outputs the composite sync signal. Serial Data (External pull-up required) This pin functins as SD, the serial data pin of the I2C interface port (see the I 2C Port Operation section for details). Serial Clock (Internal pull-up) This pin functions as the serial clock pin of the I 2C interface port (see the I 2C Port Operation section for details). I2C Address Select (Internal pull-up) This pin is the I2C Address Select, which corresponds to bits 1 and 0 of the I2C device address (see the I 2C Port Operation section for details), creating an address selection as follows: ADDR I2C Address Selected 1 1110101 = 75H = 117 0 1110110 = 76H = 118 Analog ground These pins provide the ground reference for the analog section of CH7003, and MUST be connected to the system ground, to prevent latchup. Analog Supply Voltage These pins supply the 5V power to the analog section of the CH7003. DAC Power Supply These pins supply the 5V power to CH7003's internal DACs. DAC Ground These pins provide the ground reference for CH7003's internal DACs. Digital Supply Voltage These pins supply the 3.3V power to the digital section of CH7003. Digital Ground These pins provide the ground reference for the digital section of CH7003, and MUST be connected to the system ground to prevent latchup. R (Red) Component Output This pin provides the analog Red component of the digital RGB input in the RGB Pass-Through mode. G (Green) Component Output This pin provides the analog Green component of the digital RGB input in the RGB Pass-Through mode. B (Blue) Component Output This pin provides the analog Blue component of the digital RGB input in the RGB Pass-Though mode.
23
17
Out
CSYNC
32
26
In/Out
SD
33
27
In
SC
35
29
In
ADDR
40
34
Power
AGND
37 31 29, 25 44, 36, 22, 11 42, 34, 24, 14 N/A
31 25 19,23 5,16, 30,38 8, 18, 28, 36 N/A
Power Power Power Power Power
AVDD VDD GND DVDD DGND
Out
R
N/A
N/A
Out
G
N/A
N/A
Out
B
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Digital Video Interface
CH7003B
The CH7003 digital video interface provides a flexible digital interface between a computer graphics controller and the TV encoder IC, forming the ideal quality/cost configuration for performing the TV-output function. This digital interface consists of up to 16 data signals and 4 control signals, all of which are subject to programmable control through the CH7003 register set. This interface can be configured as 8, 12 or 16-bit inputs operating in either multiplexed mode or 16-bit input operation in de-multiplexed mode. It will also accept either YCrCb or RGB (15, 16 or 24-bit) data formats. A summary of the data format modes is as follows:
Table 2. Input Data Formats
Bus Width
16-bit 15-bit 16-bit 8-bit 8-bit 8-bit 8-bit 12-bit 12-bit 16-bit
Transfer Mode
Non-multiplexed Non-multiplexed Non-multiplexed 2X-multiplexed 2X-multiplexed 3X-multiplexed 2X-multiplexed 2X-multiplexed 2X-multiplexed 2X-multiplexed
Color Space and Depth
RGB 16-bit RGB 15-bit YCrCb (24-bit) RGB 15-bit RGB 16-bit RGB 24-bit YCrCb (24-bit) RGB 24 RGB 24 RGB 24 (32)
Format Reference
5-6-5 each word 5-5-5 each word CbY0,CrY1...(CCIR656 style) 5-5-5 over two bytes 5-6-5 over two bytes 8-8-8 over three bytes Cb,Y0,Cr,Y1,(CCIR656 style) 8-8-8 over two words - `C' version 8-8-8 over two words - `I' version 8-8,8X over two words
The clock and timing signals used to latch and process the incoming pixel data is dependent upon the clock mode. The CH7003 can operate in either master (the CH7003 generates a pixel frequency which is either returned as a phase-aligned pixel clock or used directly to latch data), or slave mode (the graphics chip generates the pixel clock). The pixel clock frequency will change depending upon the active image size (e.g., 640x480 or 800x600), the desired ouput format (NTSC or PAL), and the amount of scaling desired. The pixel clock may be requested to be 1X, 2X or 3X the pixel data rate (subject to a 100 MHz frequency limitation). In the case of a 1X pixel clock the CH7003 will automatically use both clock edges if a multiplexed data format is selected. Sync Signals: Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be selected to be generated by the CH7003. In the case of CCIR656 style input, embedded sync may also be used. In each case, the horizontal timing signal (horizontal sync) must be derived from the pixel clock, with the period set to exactly 8 times (9 times for 720x400 modes) the pixel clock period, times an integer value. Each line to be set, is set up by the leading edge of Horizontal sync. The vertical timing signal must be able to be set to any integer number of lines between 420 and 836. Master Clock Mode: The CH7003 generates a clock signal (output at the P-OUT pin) which will be used by the VGA controller as a frequency reference. The VGA controller will then generate a clock signal which will be input via the XCLK input. This incoming signal will be used to latch (and de-multiplex, if required) incoming data. The XCLK input clock rate must match the input data rate, and the P-OUT clock can be requested to be 1X, 2X or 3X the pixel data rate. As an alternative, the P-OUT clock signal can also be used as the input clock signal (connected directly to the XCLK input) to latch the incoming data. If this mode is used, the incoming data must meet setup and hold times with respect to the XCLK input (with the only internal adjustment being XCLK polarity). Slave Clock Mode: The VGA controller will generate a clock which will be input to the XCLK pin (no clock signal will be output on the P-OUT pin). This signal must match the input data rate, must occur at 1X, 2X or 3X the pixel data rate, and will be used to latch (and de-multiplex if required) incoming data. Also, the graphics IC transmits back to the TV encoder the horizontal and vertical timing signals, and pixel data, each of which must meet the specified setup and hold times with respect to the pixel clock. Pixel Data: Active pixel data will be expected after a programmable number pixels times the multiplex rate after the leading edge of Horizontal Sync. In other words, specifying the horizontal back porch value (as a pixel count), plus horizontal sync width, will determine when the chip will begin to sample pixels.
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Digital Video Interface (continued) Non-multiplexed Mode
CH7003B
In the 15/16-bit mode shown in Figure 4, the pixel data bus represents a 15/16-bit non-multiplexed data stream, which contains either RGB or YCrCb formatted data. When operating in RGB mode, each 15/16-bit Pn value will contain a complete pixel encoded in either 5-6-5 or 5-5-5 format. When operating in YCrCb mode, each 16-bit Pn word will contain an 8-bit Y (luminance) value on the upper 8 bits, and an 8-bit C (color difference) value on the lower 8 bits. The color difference will be transmitted at half the data rate of the luminance data, with the sequence being set as Cb followed by Cr. The Cb and Cr data will be co-sited with the Y value transmitted with the Cb value, with the data sequence described in Table 3. The first active pixel is SAV pixels after the leading edge of horizontal sync, where SAV is a bus-controlled register.
tHSW HSYNC tHD POut/ XCLK AVR SAV Pixel Data P0a P0 P0b P1
ttSP1
SP
ttP1 P
tPH 1 PH
tHP tHP1 P1b P3 P2a P4 P2b P5
P1a P2
Figure 4: Non-multiplexed Data Transfers
Table 3. 15/16-bit Non-multiplexed Data Formats
IDF# Format
Pixel# Bus Data
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0 RGB 5-6-5
P0 R0[4] R0[3] R0[2] R0[1] R0[0] G0[5] G0[4] G0[3] G0[2] G0[1] G0[0] B0[4] B0[3] B0[2] B0[1] B0[0] P1 R1[4] R1[3] R1[2] R1[1] R1[0] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[4] B1[3] B1[2] B1[1] B1[0]
3 RGB 5-5-5
P0 x R2[4] R2[3] R2[2] R2[1] R2[0] G2[4] G2[3] G2[2] G2[1] G2[0] B2[4] B2[3] B2[2] B2[1] B2[0] P1 x R3[4] R3[3] R3[2] R3[1] R3[0] G3[4] G3[3] G3[2] G3[1] G3[0] B3[4] B3[3] B3[2] B3[1] B3[0] P0 Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] Cb0[7] Cb0[6] Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0]
1 YCrCb (16-bit)
P1 Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] Cr0[7] Cr0[6] Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0] P2 Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] Cb2[7] Cb2[6] Cb2[5] Cb2[4] Cb2[3] Cb2[2] Cb2[1] Cb2[0] P3 Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0] Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0]
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Digital Video Interface (continued)
CH7003B
When IDF = 1, (YCrCb 16-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the embedded sync will be similar to the CCIR656 convention (not identical, since that convention is for 8-bit data streams), and the first byte of the `video timing reference code' will be assumed to occur when a Cb sample would occur - if the video stream was continuous. This is delineated in Table 4 below.
Table 4. YCrCb Non-multiplexed Mode with Embedded Syncs
IDF# Format
Pixel# Bus Data
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
1 YCrCb 16-bit
P0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 P1 S[7] S[6] S[5] S[4] S[3] S[2] S[1] S[0] 0 0 0 0 0 0 0 0 P2 Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] Cb0[7] Cb0[6] Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0] P3 Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] Cr0[7] Cr0[6] Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0] P4 Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] Cb2[7] Cb2[6] Cb2[5] Cb2[4] Cb2[3] Cb2[2] Cb2[1] Cb2[0] P5 Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0] Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0] P6 Y4[7] Y4[6] Y4[5] Y4[4] Y4[3] Y4[2] Y4[1] Y4[0] Cb4[7] Cb4[6] Cb4[5] Cb4[4] Cb4[3] Cb4[2] Cb4[1] Cb4[0] P7 Y5[7] Y5[6] Y5[5] Y5[4] Y5[3] Y5[2] Y5[1] Y5[0] Cr4[7] Cr4[6] Cr4[5] Cr4[4] Cr4[3] Cr4[2] Cr4[1] Cr4[0]
In this mode, the S[7..0] byte contains the following data: S[6] S[5] S[4] = = = F V H = = = 1 during field 2, 0 during field 1 1 during field blanking, 0 elsewhere 1 during EAV (the synchronization reference at the end of active video) 0 during SAV (the synchronization reference at the start of active video)
Bits S[7] and S[3..0] are ignored.
Multiplexed Mode
Each rising edge (or each rising and falling edge) of the XCLK signal will latch data from the graphics chip. The multiplexed input data formats are shown in Figure 5 and 6. The Pixel Data bus represents an 8-, 12-, or 16-bit multiplexed data stream, which contains either RGB or YCrCb formatted data. In IDF settings of 2, 4, 5, 7, 8, and 9, the input data rate is 2X PCLK, and each pair of Pn values (e.g., P0a and P0b) will contain a complete pixel, encoded as shown in the tables below. When IDF = 6, the input data rate is 3X PCLK, and each triplet of Pn values (e.g., P0a, P0b and P0c) will contain a complete pixel, encoded as shown in the tables below. When the input is YCrCb, the color-difference data will be transmitted at half the data rate of the luminance data, with the sequence being set as Cb, Y, Cr, Y where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples -- and the following Y1 byte refers to the next luminance sample, per CCIR656 standards. However, the clock frequency is dependent upon the current mode (not 27MHz, as specified in CCIR656.)
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Digital Video Interface (continued)
CH7003B
tHSW HS tHD XCLK
DEC = 0
tP2
tPH2
tSP2
tHP2
XCLK
DEC = 1
tSP2
tHP2
tSP2
tHP2
D[15:0]
P0a
P0b
P1a
P1b
P2a
P2b
Figure 5: Multiplexed Pixel Data Transfer Mode
Table 5. RGB 8-bit Multiplexed Mode
IDF# Format
Pixel# Bus Data D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a G0[2] G0[1] G0[0] B0[4] B0[3] B0[2] B0[1] B0[0]
7 RGB 5-6-5
P0b R0[4] R0[3] R0[2] R0[1] R0[0] G0[5] G0[4] G0[3] P1a G1[2] G1[1] G1[0] B1[4] B1[3] B1[2] B1[1] B1[0] P1b R1[4] R1[3] R1[2] R1[1] R1[0] G1[5] G1[4] G1[3] P0a G0[2] G0[1] G0[0] B0[4] B0[3] B0[2] B0[1] B0[0]
8 RGB 5-5-5
P0b x R0[4] R0[3] R0[2] R0[1] R0[0] G0[4] G0[3] P1a G1[2] G1[1] G1[0] B1[4] B1[3] B1[2] B1[1] B1[0] P1b x R1[4] R1[3] R1[2] R1[1] R1[0] G1[4] G1[3]
Table 6. RGB 12-bit Multiplexed Mode
IDF# Format Pixel# Bus Data D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a G0[3] G0[2] G0[1] G0[0] B0[7] B0[6] B0[5] B0[4] B0[3] B0[2] B0[1] B0[0] 4 12-bit RGB (12-12) P0b R0[7] R0[6] R0[5] R0[4] R0[3] R0[2] R0[1] R0[0] G0[7] G0[6] G0[5] G0[4] P1a G1[3] G1[2] G1[1] G1[0] B1[7] B1[6] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] P1b R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] G1[7] G1[6] G1[5] G1[4] P0a G0[4] G0[3] G0[2] B0[7] B0[6] B0[5] B0[4] B0[3] G0[0] B0[2] B0[1] B0[0] 5 12-bit RGB (12-12) P0b R0[7] R0[6] R0[5] R0[4] R0[3] G0[7] G0[6] G0[5] R0[2] R0[1] R0[0] G0[1] P1a G1[4] G1[3] G1[2] B1[7] B1[6] B1[7] B1[4] B1[3] G1[0] B1[2] B1[1] B1[0] P1b R1[7] R1[6] R1[5] R1[4] R1[3] G1[7] G1[6] G1[5] R1[2] R1[1] R1[0] G1[1]
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Digital Video Interface (continued)
Table 7. RGB 16-bit Muliplexed Mode
IDF# Format
Pixel# Bus Data D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a G0[7] G0[6] G0[5] G0[4] G0[3] G0[2] G0[1] G0[0] B0[7] B0[6] B0[5] B0[4] B0[3] B0[2] B0[1] B0[0]
CH7003B
2 16-bit RGB (16-8)
P0b A0[7] A0[6] A0[5] A0[4] A0[3] A0[2] A0[1] A0[0] R0[7] R0[6] R0[5] R0[4] R0[3] R0[2] R0[1] R0[0] P1a G1[7] G1[6] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[7] B1[6] B1[5] B1[4] B1[3] B1[2] B0[1] B0[0] P1b A1[7] A1[6] A1[5] A1[4] A1[3] A1[2] A1[1] A1[0] R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0]
Note: The AX[7:0] data is ignored.
Table 8. YCrCb Multiplexed Mode
IDF# Format Pixel# Bus Data D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a Cb0[7] Cb0[6] Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0] P0b Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] P1a Cr0[7] Cr0[6] Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0] 9 YCrCb 8-bit P1b Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] P2a Cb2[7] Cb2[6] Cb2[5] Cb2[4] Cb2[3] Cb2[2] Cb2[1] Cb2[0] P2b Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] P3a Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0] P3b Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0]
When IDF = 9 (YCrCb 8-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the embedded sync will follow the CCIR656 convention, and the first byte of the "video timing reference code" will be assumed to occur when a Cb sample would occur if the video stream was continuous. This is delineated in Table 9.
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Digital Video Interface (continued)
Table 9. YCrCb Multiplexed Mode with Embedded Syncs
IDF# Format
Pixel# Bus Data D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a 1 1 1 1 1 1 1 1 P0b 0 0 0 0 0 0 0 0 P1a 0 0 0 0 0 0 0 0
CH7003B
9 YCrCb 8-bit
P1b S[7] S[6] S[5] S[4] S[3] S[2] S[1] S[0] P2a Cb2[7] Cb2[6] Cb2[5] Cb2[4] Cb2[3] Cb2[2] Cb2[1] Cb2[0] P2b Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] P3a Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0] P3b Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0]
In this mode, the S[7..0] byte contains the following data: S[6] S[5] S[4] = = = F V H = = = 1 during field 2, 0 during field 1 1 during field blanking, 0 elsewhere 1 during EAV (the synchronization reference at the end of active video) 0 during SAV (the synchronization reference at the start of active video)
Bits S[7] and S[3..0] are ignored.
tHSW HSYNC tHD POut/ XCLK tSP3 Pixel D[7:0] Data P0a P0b tHP3 P0c P1a P1b P1c tP3 tPH3
Figure 6: Multiplexed Pixel Data Transfer Mode (IDF = 6)
Table 10. RGB 8-bit Multiplexed Mode (24-bit Color)
IDF# Format
Pixel# Bus Data D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a B0[7] B0[6] B0[5] B0[4] B0[3] B0[2] B0[1] B0[0] P0b G0[7] G0[6] G0[5] G0[4] G0[3] G0[2] G0[1] G0[0] P0c R0[7] R0[6] R0[5] R0[4] R0[3] R0[2] R0[1] R0[0] P1a B1[7] B1[6] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0]
6 RGB 8-bit
P1b G1[7] G1[6] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] P1c R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] P2a B2[7] B2[6] B2[5] B2[4] B2[3] B2[2] B2[1] B2[0] P2b G2[7] G2[6] G2[5] G2[4] G2[3] G2[2] G2[1] G2[0] P2C R2[7] R2[6] R2[5] R2[4] R2[3] R2[2] R2[1] R2[0]
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Functional Description
CH7003B
The CH7003 is a TV-output companion chip to graphics controllers providing digital output in either YUV or RGB format. This solution involves both hardware and software elements which work together to produce an optimum TV screen image based on the original computer generated pixel data. All essential circuitry for this conversion are integrated on-chip. On-chip circuitry includes memory, memory control, scaling, PLL, DAC, filters, and NTSC/PAL encoder. All internal signal processing, including NTSC/PAL encoding, is performed using digital techniques to ensure that the high-quality video signals are not affected by drift issues associated with analog components. No additional adjustment is required during manufacturing. CH7003 is ideal for PC motherboards, web browsers, or VGA add-in boards where a minimum of discrete support components (passive components, parallel resonance 14.31818 MHz crystal) are required for full operation.
Architectural Overview
The CH7003 is a complete TV output subsystem which uses both hardware and software elements to produce an image on TV which is virtually identical to the image that would be displayed on a monitor. Simply creating a compatible TV output from a VGA input involves a relatively straightforward process. This process includes a standard conversion from RGB to YUV color space, converting from a non-interlaced to an interlaced frame sequence, and encoding the pixel stream into NTSC or PAL compliant format. However, creating an optimum computer-generated image on a TV screen involves a highly sophisticated process of scaling, deflickering, and filtering. This results in a compatible TV output that displays a sharp and subtle image, of the right size, with minimal artifacts from the conversion process. As a key part of the overall system solution, the CH7003 software establishes the correct framework for the VGA input signal to enable this process. Once the display is set to a supported resolution (either 640x480 or 800x600), the CH7003 software may be invoked to establish the appropriate TV output display. The software then programs the various timing parameters of the VGA controller to create an output signal that will be compatible with the chosen resolution, operating mode, and TV format. Adjustments performed in software include pixel clock rates, total pixels per line, and total lines per frame. By performing these adjustments in software, the CH7003 can render a superior TV image without the added cost of a full frame buffer memory - normally used to implement features such as scaling and full synchronization. The CH7003 hardware accepts digital RGB or YCrCb inputs, which are latched in synchronization with the pixel clock. These inputs are then color-space converted into YUV in 4-2-2 format and stored in a line buffer memory. The stored pixels are fed into a block where scan-rate conversion, underscan scaling and 2-line, 3-line, 4-line and 5line vertical flicker filtering are performed. The scan-rate converter transforms the VGA horizontal scan-rate to either NTSC or PAL scan rates; the vertical flicker filter eliminates flicker at the output while the underscan scaling reduces the size of the displayed image to fit onto a TV screen. The resulting YUV signals are filtered through digital filters to minimize aliasing problems. The digital encoder receives the filtered signals and transforms them to composite and S-Video outputs, which are converted by the three 9-bit DACs into analog outputs.
Color Burst Generation*
The CH7003 allows the sub-carrier frequency to be accurately generated from a 14.31818 MHz crystal oscillator, leaving the sub-carrier frequency independent of the sampling rate. As a result, the CH7003 may be used with any VGA chip (with an approprate digital interface) since the CH7003 sub-carrier frequency can be generated without being dependent on the precise pixel rates of VGA controllers. This feature is a significant benefit, since even a 0.01% sub-carrier frequency variation may be enough to cause some television monitors to lose color lock. In addition, the CH7003 has the capability to genlock the color burst signal to the VGA horizontal sync frequency, which enables a fully synchronous system between the graphics controller and the television. When genlocked, the CH7003 can also stop "dot crawl" motion (for composite mode operation, in NTSC modes) to eliminate the annoyance of moving borders. Both of these features are under programmable control through the register set.
Display Modes
The CH7003 display mode is controlled by three independent factors: input resolution, TV format, and scale factor, which are programmed via the display mode register. It is designed to accept input resolutions of 640x480, 800x600, 640x400 (including 320x200 scan-doubled output), 720x400, and 512x384. It is designed to support
12
*Patent number 5,874,846
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Display Modes (continued)
CH7003B
output to either NTSC or PAL television formats. The CH7003 provides interpolated scaling with selectable factors of 5:4, 1:1, 7:8, 5:6, 3:4 and 7:10 in order to support adjustable overscan or underscan operation when displayed on a TV. This combination of factors results in a matrix of useful operating modes which are listed in detail in Table 11.
Table 11. CH7003 Display Modes
TV Format Standard
NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL
Input (active) Resolution
640x480 640x480 640x480 800x600 800x600 800x600 640x400 640x400 640x400 720x400 720x400 512x384 512x384 640x480 640x480 640x480 800x600 800x600 800x600 640x400 640x400 720x400 720x400 512x384 512x384
Scale Factor
1:1 7:8 5:6 5:6 3:4 7:10 5:4 1:1 7:8 5:4 1:1 5:4 1:1 5:4 1:1 5:6 1:1 5:6 3:4 5:4 1:1 5:4 1:1 5:4 1:1
Active TV Lines
480 420 400 500 450 420 500 400 350 500 400 480 384 600 480 400 600 500 450 500 400 500 400 480 384
Percent (1) Overscan
10% (3%) (8%) 16% 4% (3%) 16% (8%) (19%) 16% (8%) 10% (11%) 14% (8%) (29%) 14% (4%) (15%) (4%) (29%) (4%) (29%) (8%) (35%)
Pixel Clock
24.671 28.196 30.210 39.273 43.636 47.832 21.147 26.434 30.210 23.790 29.455 20.140 24.671 21.000 26.250 31.500 29.500 36.000 39.000 25.000 31.500 28.125 34.875 21.000 26.250
Horizontal Total
784 784 800 1040 1040 1064 840 840 840 945 936 800 784 840 840 840 944 960 936 1000 1008 1125 1116 840 840
Vertical Total
525 600 630 630 700 750 420 525 600 420 525 420 525 500 625 750 625 750 836 500 625 500 625 500 625
(1) Note: Percent underscan is a calculated value based on average viewable lines on each TV format, assuming an average TV ovescan of 10%. (Negative values) indicate modes which are operating in underscan. For NTSC: 480 active lines - 10% (overscan) = 432 viewable lines (average) For PAL: 576 active lines - 10% (overscan) = 518 viewable lines (average)
The inclusion of multiple levels of scaling for each resolution have been created to enable optimal use of the CH7003 for different application needs. In general, underscan (modes where percent overscan is negative) provides an image that is viewable in its entirety on screen; it should be used as the default for most applications (e.g., viewing text screens, operating games, running productivity applications, working within Windows). Overscanning provides an image that extends past the edges of the TV screen, exactly like normal television programs and movies appear on TV, and is only recommended for viewing movies or video clips coming from the computer.
Anti-flicker Filter
The CH7003 integrates an advanced 4-line (3-line for 1:1 modes) vertical deflickering filter circuit to help eliminate the flicker associated with interlaced displays. When operating in scaled display modes, this flicker circuit provides an adaptive filter algorithm for implementing flicker reduction with selections of high or low flicker content. When operating in scale factors other than (1:1) display modes, it provides a selection of high or low flicker content. When operating in non-scaled (1:1) display modes, it provides a selection of four anti-flicker filter modes (non-filtering
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Anti-flicker Filter (continued)
CH7003B
and three levels of flicker filtering). These modes are fully programmable via I2C, and are listed under the flicker filter register.
Internal Voltage Reference
An on-chip bandgap circuit is used in the DAC to generate a reference voltage which, in conjunction with a reference resistor at pin RSET, and register controlled divider, sets the output ranges of the DACs. The CH7003 bandgap reference voltage is 1.235 volts nominal for NTSC or PAL-M, or 1.317 volts nominal (for PAL or NTSCJ), which is determined by IDF register bit 6 (DACG bit). The recommended value for the reference resistor RSET is 360 ohms (though this may be adjusted in order to achieve a different output level). The gain setting for DAC output is 1/48 th. Therefore, for each DAC, the current output per LSB step is determined by the following equation: ILSB = V(RSET)/RSET reference resistor* 1/GAIN For DACG=0, this is: ILSB = 1.235/360 * 1/48 = 71.4 A (nominal) For DACG=1, this is: ILSB = 1.317/360 * 1/48 = 76.2 A (nominal)
Power Management
The CH7003 supports five operating states including Normal [On], Power Down, Full Power Down, S-Video Off, and Composite Off to provide optimal power consumption for the application involved. Using the programmable power down modes accessed over the I2C port, the CH7003 may be placed in either Normal state, or any of the four power managed states, as listed below (see "Power Management Register" under the Register Descriptions section for programming information). To support power management, a TV sensing function (see "Connection Detect Register" under the Register Descriptions section) is provided, which identifies whether a TV is connected to either S-Video or composite (or neither). This sensing function can then be used to enter into the appropriate operating state (e.g., if TV is sensed only on composite, the S-Video Off mode could be set by software).
Table 12. Power Management
Operating State
Normal (On): Power Down:
Functional Description
In the normal operating state, all functions and pins are active In the power-down state, most pins and circuitry are disabled.The BCO pin will continue to provide either the VCO divided by K3, or 14.318 MHz out. Power is shut off to the unused DAC's associated with S-Video outputs. In Composite-off state, power is shut off to the unused DAC associated with CVBS output. In this power-down state, all but the I2C circuits are disabled. This places the CH7003 in its lowest power consumption mode.
S-Video Off: Composite Off: Full Power Down:
Luminance and Chrominance Filter Options
The CH7003 contains a set of luminance filters to provide a controllable bandwidth output on both CVBS and S-Video outputs. All values are completely programmable via the Video Bandwidth Register. For all graphs shown, the horizontal axis is frequency in MHz, and the vertical axis is gain in dBs. The composite luminance and chrominance video bandwidth output is shown in Table 13.
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Luminance and Chrominance Filter Options (continued)
Table 13. Video Bandwidth
Mode Chrominance Bandwidth(MHz) CBW[1:0] 01 10 0.68 0.80 0.85 1.00 0.58 0.68 0.71 0.83 0.91 1.07 1.13 1.32 0.77 0.90 0.95 1.12 0.81 0.95 1.02 1.20 0.68 0.80 0.86 1.00 0.98 1.15 0.68 0.80 0.85 1.00 1.02 1.20 0.71 0.83 0.81 0.95 0.87 1.02 0.85 1.00 1.03 1.22 1.12 1.32 0.85 0.99 0.94 1.11 1.03 1.21
CH7003B
Luminance Bandwidth with Sin(X) /X (MHz) CVBS S-Video S-Video YCV 0 2.26 2.82 1.93 2.36 3.03 3.75 2.56 3.17 2.69 3.39 2.28 2.84 3.25 2.26 2.82 3.39 2.35 2.70 2.89 2.82 3.44 3.73 2.82 3.13 3.43 1 3.37 4.21 2.87 3.52 4.51 5.59 3.81 4.72 4.01 5.05 3.39 4.24 4.84 3.37 4.21 5.05 3.50 4.02 4.31 4.20 5.13 5.56 4.20 4.66 5.11 YSV[1:0], YPEAK = 0 00 01 1X 2.26 3.37 5.23 2.82 4.21 6.53 1.93 2.87 4.46 2.36 3.52 5.46 3.03 4.51 7.00 3.75 5.59 8.68 2.56 3.81 5.92 3.17 4.72 7.33 2.69 4.01 6.22 3.39 5.05 7.84 2.28 3.39 5.26 2.84 4.24 6.58 3.25 4.84 7.52 2.26 3.37 5.23 2.82 4.21 6.53 3.39 5.05 7.84 2.35 3.50 5.43 2.70 4.02 6.24 2.89 4.31 6.68 2.82 4.20 6.53 3.44 5.13 7.97 3.73 5.56 8.63 2.82 4.20 6.52 3.13 4.66 7.24 3.43 5.11 7.94 YSV[1:0], YPEAK = 1 00 01 1X 2.57 4.44 5.23 3.21 5.56 6.53 2.19 3.79 4.46 2.68 4.64 5.46 3.44 5.95 7.00 4.27 7.38 8.68 2.91 5.04 5.92 3.60 6.23 7.33 3.06 5.29 6.22 3.85 6.67 7.84 2.59 4.48 5.26 3.23 5.59 6.58 3.70 6.39 7.52 2.57 4.44 5.23 3.21 5.56 6.53 3.85 6.67 7.84 2.67 4.62 5.43 3.07 5.30 6.24 3.29 5.68 6.68 3.21 5.55 6.53 3.92 6.77 7.97 4.24 7.34 8.63 3.20 5.54 6.52 3.56 6.16 7.24 3.90 6.75 7.94
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
00 0.62 0.78 0.53 0.65 0.83 1.03 0.70 0.87 0.74 0.93 0.63 0.78 0.89 0.62 0.78 0.93 0.64 0.74 0.79 0.77 0.95 1.02 0.77 0.86 0.94
11 0.95 1.18 0.81 0.99 1.27 1.57 1.07 1.33 1.13 1.42 0.95 1.19 1.36 0.95 1.18 1.42 0.98 1.13 1.21 1.18 1.44 1.56 1.18 1.31 1.44
The composite luminance and chrominance frequency response is depicted in Figure 7 through 9.
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CHRONTEL
Luminance and Chrominance Filter Options (continued)
0 0
CH7003B
-66
12 -12
(YCVdB YCVdB
< i>
18 -18 )n n 24 -24
-30 30 -36 36
42 -42 0
0
11
22
33
44
5 5 f 66 n,i fn , i
6
77
88
9 9
10 10
11 11
12 12
106
10
6
Figure 7: Composite Luminance Frequency Response (YCV = 0)
0
0
6 -6
-12 12
18 -18 YSVdB (YSVdB)nn 24 -24
30 -30
36 -36
42 -42 0 0
1 1
2 2
3 3
4 4
5 5
6 6 fn,ifn , i
10 10 6 6
7 7
8 8
9 9
10 10
11 11
12 12
Figure 8: S-Video Luminance Frequency Response (YSV = 1X, YPEAK = 0)
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Luminance and Chrominance Filter Options (continued)
CH7003B
0 0
-66
-12 12
18 -18
(UVfirdB)n 24 -24
UVfirdB n
30 -30
36 -36
42 -42
0 0
1 1
2 2
3 3
4 4
5 5
6 6 f fn,i , i n
7 7
8 8
9
10 10
11 11
12 12
106 6 10
Figure 9: Chrominance Frequency Response
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CHRONTEL
NTSC and PAL Operation
CH7003B
Composite and S-Video outputs are supported in either NTSC or PAL format. The general parameters used to characterize these outputs are listed in Table 14 and shown in Figure 10. (See Figure 13 through 18 for illustrations of composite and S-Video output waveforms.)
CCIR624-3 Compliance
The CH7003 is predominantly compliant with the recommendations called out in CCIR624-3. The following are the only exceptions to this compliance: * The frequencies of Fsc, Fh, and Fv can only be guaranteed in master or psuedo-master modes, not in slave mode when the graphics device generates these frequencies. * It is assumed that gamma correction, if required, is performed in the graphics device which establishes the color reference signals. * All modes provide the exact number of lines called out for NTSC and PAL modes respectively, except mode 21, which outputs 800x600 resolution, scaled by 3:4, to PAL format with a total of 627 lines (vs. 625). * Chroma signal frequency response will fall within 10 % of the exact recommended value. * Pulse widths and rise/fall times for sync pulses, front/back porches, and equalizing pulses are designed to approximate CCIR624-3 requirements, but will fall into a range of values due to the variety of clock frequencies used to support multiple operating modes.
Table 14. NTSC/PAL Composite Output Timing Parameters (in S)
Symbol Description NTSC
A B C D E F G H Front Porch Horizontal Sync Breezeway Color Burst Back Porch Black Active Video Black 287 0 287 287 287 340 340 340
Level (mV) PAL
300 0 300 300 300 300 300 300
Duration (uS) NTSC
1.49 - 1.51 4.69 - 4.72 0.59 - 0.61 2.50 - 2.53 1.55 - 1.61 0.00 - 7.50 37.66 - 52.67 0.00 - 7.50
PAL
1.48 - 1.51 4.69 - 4.71 0.88 - 0.92 2.24 - 2.26 2.62 - 2.71 0.00 - 8.67 34.68 - 52.01 0.00 - 8.67
For this table and all subsequent figures, key values are:
Note: 1. 2. 3. 4. RSET = 360 ohms; V(RSET) = 1.235V; 75 ohms doubly terminated load. Durations vary slightly in different modes due to the different clock frequencies used. Active video and black (F, G, H) times vary greatly due to different scaling ratios used in different modes. Black times (F and H) vary with position controls.
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CH7003B
A
B
C
D
E
F
G
H
Figure 10: NTSC / PAL Composite Output
START START OF O F VS NC V YN SY C A AL G N StartA N L O of A O G field FIELD 1 1 FIELD 1
523 520 520
524 521 521
525 522 522
523 523 1
524 524 2
3 525 525
1 1 4
2 2 5
36 3
4 4 7
58 5
9 6 6
10 7 7
11 8 8
12 9 9
Pre-equalizing pulse interval
Vertical sync pulse interval
Post-equalizing pulse interval
Reference Line AN LO phase A AL G NA O vertical sub-carrierG FIELD 1 FIELD 2 t1+V interval color field 2
261 258 258
262 259 259
263 260 260
264 261 261 Start of field 2
265 262 262
266 263 263
267 264 264
268 265 265
269 266 266
270 267 267
271 268 268
272 269 269
273 270 270
274 271 271
275 272 272
Reference A AO NL G sub-carrier phase FIELD 1 t2+V color field 2
START O F VYC SN
523 520
524 521
525 522
523 1 Start of field 3
2 524
525 3
4 1
5 2
6 3
7 4
8 5
9 6
10 7
11 8
12 9
Reference G A AO NL sub-carrier phase FIELD 2 t3+V color field 3
261 258
262 259
263 260
264 261 Start of field 4
262 265
266 263
264 267
265 268
269 266
270 267
268 271
272 269
273 270
274 271
272 275
Reference sub-carrier phase color field 4
Figure 11: Interlaced NTSC Video Timing
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SA T TR O F VYC SN A AO NL G FIELD 1
CH7003B
620 620
621 621
622 622
623 623
624
625
1
2
3
4
5
6 6
7 7
8 8
9 9
10 10
A AO NL G FIELD 2
308 308
309 309
310 310
311 311
312
313
314
315
316
317
318 318
319 319
320 320
321 321
322 322
323 323
A AO NL G FIELD 3
620 620
621 621
622 622
623 623
624
625
1
2
3
4
5
6 6
7 7
8 8
9 9
10 10
A AO NL G FIELD 4
308 308
309 309
310 310
311 311
312
313
314
315
316
317
318 318
319 319
320 320
321 321
322 322
323 323
B RS BU ST UR T B AN I G BL NKN LA KI G N INTERVALS
4 3S B RS P AS = R FE EN E P A E = 1 5 EL TI E T U H 35 LA IV O BU ST PH SE = RE ER NC P A E = 13 RE ATVE TO U UR T HA E EF RE CE H S R P L S IT H = 0 + C MP N N ET PA SWTC = 0, +V CO PO E T AL WI CH , V OM ON N 2
B RS P AS = R FE E CE P AS +9 2 5 R LA IV T U E C 1 A E 0 = 25 EL TI E O H BU ST PH SE = RE ER N E PH SE+90 22 RE ATVE TO U UR T HA E EF R N = P L S IT H = 1 -V C MP N N ET PA SWTC = 1, -V CO PO E T AL WI CH , OM ON N
Figure 12: Interlaced PAL Video Timing
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CH7003B
Black Blue Red Magenta
Green Cyan Yellow
White
Color/Level White Yellow
mA 26.66 24.66
V 1.000 0.925
Color bars:
Cyan Green Magenta Red Blue Black Blank
21.37 19.37 16.22 14.22 11.08 9.08 7.65
0.801 0.726 0.608 0.533 0.415 0.340 0.287
Sync
0.00
0.000
Figure 13: NTSC Y (Luminance) Output Waveform (DACG = 0)
Blue Red Magenta
Green Cyan Yellow
White
Black
Color/Level White Yellow
mA 26.75 24.62
V 1.003 0.923
Color bars:
Cyan Green Magenta Red Blue Blank/Black
21.11 18.98 15.62 13.49 10.14 8.00
0.792 0.712 0.586 0.506 0.380 0.300
Sync
0.00
0.000
Figure 14: PAL Y (Luminance) Video Output Waveform (DACG = 1)
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CH7003B
Magenta
Yellow
Green
White
Black
Cyan
Color bars:
Color/Level Cyan/Red Green/Magenta mA 25.80 25.01 V 0.968 0.938
Blue
Red
Yellow/Blue
22.44
0.842
Peak Burst Blank Peak Burst
18.08 14.29 10.51
0.678 0.536 0.394
3.579545 MHz Color Burst (9 cycles)
Yellow/Blue 6.15 0.230
Green/Magenta Cyan/Red
3.57 2.79
0.134 0.105
Figure 15: NTSC C (Chrominance) Video Output Waveform (DACG = 0)
Magenta
Yellow
White
Green
Black
Cyan
Color bars:
Color/Level Cyan/Red Green/Magenta mA 27.51 26.68 V 1.032 1.000
Blue
Red
Yellow/Blue
23.93
0.897
Peak Burst Blank Peak Burst
19.21 15.24 11.28
0.720 0.572 0.423
4.433619 MHz Color Burst (10 cycles)
Yellow/Blue 6.56 0.246
Green/Magenta Cyan/Red
3.81 2.97
0.143 0.111
Figure 16: PAL C (Chrominance) Video Output Waveform (DACG = 1)
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CH7003B
Magenta
Yellow
Green
White
Black
Cyan
Blue
Red
Color/Level Peak Chrome White
mA 32.88 26.66
V 1.233 1.000
Color bars:
Peak Burst Black Blank
11.44 9.08 7.65
0.429 0.340 0.281
Peak Burst
4.450
0.145
3.579545 MHz Color Burst (9 cycles)
Sync 0.00 0.000
Figure 17: Composite NTSC Video Output Waveform (DACG = 0)
Magenta
Yellow
Green
White
Black
Cyan
Blue
Red
Color/Level Peak Chrome White
mA
V
Color bars:
33.31 1.233 26.75 1.003
Peak Burst
11.97
0.449
Blank/Black
8.00
0.300
Peak Burst
4.04 0.00
0.151 0.000
Sync
4.433619 MHz Color Burst (10 cycles)
Figure 18: Composite PAL Video Output Waveform (DACG = 1)
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CHRONTEL
I2C Port Operation
CH7003B
The CH7003 contains a standard I2C control port, through which the control registers can be written and read. This port is comprised of a two-wire serial interface, pins SD (bi-directional) and SC, which can be connected directly to the SDB and SCB buses as shown in Figure 19. The Serial Clock line (SC) is input only and is driven by the output buffer of the master device (also shown in Figure 19). The CH7003 acts as a slave, and generation of clock signals on the bus is always the responsibility of the master device. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data on the bus can be transferred up to 400 kbit/s.
+VDD RP
SDB (Serial Data Bus) SCB (Serial Clock Bus) SC DATAN2 OUT MASTER SCLK OUT FROM MASTER SD
DATAN2 OUT
DATAN2 OUT
DATA IN MASTER BUS MASTER
SCLK IN1 SLAVE
DATA IN1
SCLK IN2 SLAVE
DATA IN2
Figure 19: Connection of Devices to the Bus
Electrical Characteristics for Bus Devices
The electrical specifications of the bus devices' inputs and outputs and the characteristics of the bus lines connected to them are shown in Figure 19. A pull-up resistor (RP) must be connected to a 5V 10% supply. The CH7003 is a device with input levels related to VDD.
Maximum and minimum values of pull-up resistor (R P)
The value of RP depends on the following parameters: * Supply voltage * Bus capacitance * Number of devices connected (input current + leakage current = Iinput) The supply voltage limits the minimum value of resistor R P due to the specified minimum sink current of 3mA at VOLmax = 0.4 V for the output stages: RP >= (VDD - 0.4) / 3 (RP in k) The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum value of RP due to the specified rise time. The equation for RP is shown below: RP <= 103/C (where: RP is in k and C, the total capacitance, is in pF) The maximum HIGH level input current of each input/output connection has a specified maximum value of 10 A. Due to the desired noise margin of 0.2VDD for the HIGH level, this input current limits the maximum value of R P. The RP limit depends on VDD and is shown below: RP <= (100 x VDD)/ Iinput (where: RP is in k and Iinput is in A)
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Transfer Protocol
CH7003B
Both read and write cycles can be executed in "Alternating" and "Auto-increment" modes. Alternating mode expects a register address prior to each read or write from that location (i.e., transfers alternate between address and data). Auto-increment mode allows you to establish the initial register location, then automatically increments the register address after each subsequent data access (i.e., transfers will be address, data, data, data...). A basic serial port transfer protocol is shown in Figure 20 and described below.
SD
I2C
SC Start Condition
1-7
8
9
1-8
9
1-8
9
Device ID
R/W*
ACK
CH7003 acknowledge
Data1
ACK
CH7003 acknowledge
Data n
CH7003 acknowledge
ACK
Stop Condition
Figure 20: Serial Port Transfer Protocol 1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high; this is the "START" condition. Transitions of address and data bits can only occur while SC is low. 2. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high; this is the "STOP" condition. 3. Upon receiving the first START condition, the CH7003 expects a Device Address Byte (DAB) from the master device. The value of the device address is shown in the DAB data format below. 4. After the DAB is received, the CH7003 expects a Register Address Byte (RAB) from the master. The format of the RAB is shown in the RAB data format below (note that B7 is not used).
Device Address Byte (DAB)
B7
1
B6
1
B5
1
B4
0
B3
1
B2
ADDR*
B1
ADDR
B0
R/W
5. After the DAB is received, the CH7003 expects a Register Address Byte (RAB) from the master. The format of the RAB is shown in the RAB data format below (note that B7 is not used).
R/W Read/Write Indicator
"0": "1":
master device will write to the CH7003 at the register location specified by the address AR[5:0] master device will read from the CH7003 at the register location specified by the address AR[5:0].
Register Address Byte (RAB)
B7
1
B6
AutoInc
B5
AR[5]
B4
AR[4]
B3
AR[3]
B2
AR[2]
B1
AR[1]
B0
AR[0]
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CHRONTEL
Transfer Protocols (continued)
AutoInc
CH7003B
Register Address Auto-Increment - to facilitate sequential R/W of registers.
"1":
Auto-Increment enabled (auto-increment mode).
Write: After writing data into a register, the Address Register will automatically be incremented by one. Read: Before loading data from a register to the on-chip temporary register (getting ready to be serially read), the Address Register will automatically be incremented by one. However, for the first read after an RAB, the Address Register will not be changed. "0": Auto-Increment disabled (alternating mode).
Write: After writing data into a register, the Address Register will remain unchanged until a new RAB is written. Read: Before loading data from a register to the on-chip temporary register (getting ready to be serially read), the Address Register will remain unchanged.
AR[5:0] Specifies the Address of the Register to be Accessed.
This register address is loaded into the Address Register of the CH7003. The R/W access, which follows, is directed to the register specified by the content stored in the Address Register. The following two sections describe the operation of the serial interface for the four combinations of R/W = 0,1 and AutoInc = 0,1.
CH7003 Write Cycle Protocols (R/W = 0)
Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the mastertransmitter. The master-transmitter releases the SD line (HIGH) during the acknowledge clock pulse. The slavereceiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW during the HIGH period of the clock pulse. The CH7003 always acknowledges for writes (see Figure 21). Note that the resultant state on SD is the wired-AND of data outputs from the transmitter and receiver.
SD Data Output By Master-Transmitter not acknowledge SD Data Output By the CH7003 SC from Master Start Condition 1 2 acknowledge 8 9
clock pulse for acknowledgement
Figure 21: Acknowledge on the Bus
Figure 22 shows two consecutive alternating write cycles for AutoInc = 0 and R/W = 0. The byte of information, following the Register Address Byte (RAB), is the data to be written into the register specified by AR[5:0]. If AutoInc = 0, then another RAB is expected from the master device, followed by another data byte, and so on.
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Transfer Protocols (continued)
CH7003 acknowledge CH7003 acknowledge CH7003 acknowledge CH7003 acknowledge
CH7003B
CH7003 acknowledge
SD
I2C
SC Start Condition
1-7
8
9
1-8
9
1-8
9
1-8
9
1-8
9
Device ID
R/W*
ACK
RAB
ACK
Data
ACK
RAB
ACK
Data
ACK
Stop Condition
Figure 22: Alternating Write Cycles
Note: The acknowledge is from the CH7003 (slave).
If AutoInc = 1, then the register address pointer will be incremented automatically and subsequent data bytes will be written into successive registers without providing an RAB between each data byte. An Auto-increment write cycle is shown in Figure 23.
SD
CH7003 acknowledge
CH7003 acknowledge
CH7003 acknowledge
CH7003 acknowledge
I2C
SC Start Condition
1-7
8
9
1-8
9
1-8
9
1-8
9
Device ID
R/W*
ACK
RAB n
ACK
Data n
ACK
Data n+1
ACK
Stop Condition
Figure 23: Auto-Increment Write Cycle
Note: The acknowledge is from the CH7003 (slave).
When the auto-increment mode is enabled (AutoInc is set to 1), the register address pointer continues to increment for each write cycle until AR[5:0] = 2A (2A is the address of the Address Register). The next byte of information represents a new auto-sequencing "Starting address," which is the address of the register to receive the next byte. The auto-sequencing then resumes based on this new "Starting address." The auto-increment sequence can be terminated any time by either a "STOP" or "RESTART" condition. The write operation can be terminated with a "STOP" condition.
CH7003 Read Cycle Protocols (R/W = 1)
If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter CH7003 releases the data line to allow the master to generate the STOP condition or the RESTART condition. To read the content of the registers, the master device starts by issuing a "START" condition (or a "RESTART" condition). The first byte of data, after the START condition, is a DAB with R/W = 0. The second byte is the RAB with AR[5:0], containing the address of the register that the master device intends to read from in AR[5:0]. The master device should then issue a "RESTART" condition ("RESTART" = "START," without a previous "STOP" condition). The first byte of data, after this RESTART condition, is another DAB with R/W=1, indicating the master's intention to read data hereafter. The master then reads the next byte of data (the content of the register specified in the RAB). If AutoInc = 0, then another RESTART condition, followed by another DAB with R/W = 0 and RAB, is expected from the master device. The master device then issues another RESTART, followed by another DAB. After that, the master may read another data byte, and so on. In summary, a RESTART condition, followed by a DAB, must be produced by the master before each of the RAB, and before each of the data read events. Two consecutive alternating read cycles are shown in Figure 24.
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Transfer Protocols (continued)
.
CH7003B
CH7003 acknowledge
CH7003 acknowledge
CH7003 acknowedge
SD
I2C I2C
Master does not acknowledge
SC Start Condition
1-7
8
9
1-8
9
10
1-7
8
9
1-8
9
10
Device ID R/W*
ACK
RAB 1
ACK
Restart Condition
Device ID R/W*
ACK
Data 1
ACK
Restart Condition
Master does not acknowledge CH7003 acknowledge CH7003 acknowledge CH7003 acknowledge
I2 C
I2C
1-7
8
9
1-8
9
10
1-7
8
9
1-8
9
Device ID
R/W*
ACK
RAB 2
ACK
Restart Device ID Condition
R/W*
ACK
Data 2
ACK
Stop Condition
Figure 24: Alternating Read Cycle
If AutoInc = 1, then the address register will be incremented automatically and subsequent data bytes can be read from successive registers, without providing a second RAB.
CH7003 acknowledge
CH7003
CH7003 acknowledge
Master acknowledge
Master does not acknowledge just before Stop condition
SD
I2C
I2 C
SC
1-7
8
9
1-8
9
10
1-7
8
9
1-8
9
1-8
9
Start Device ID R/W* Condition
ACK
RAB n
ACK
Restart Device ID R/W* Condition
ACK
Data n
ACK
Data n+1
ACK
Stop Condition
Figure 25: Auto-increment Read Cycle
When the auto-increment mode is enabled (AutoInc is set to 1), the Address Register will continue incrementing for each read cycle. When the content of the Address Register reaches 2A, it will wrap around and start from 00h again. The auto increment sequence can be terminated by either a "STOP" or "RESTART" condition. The read operation can be terminated with a "STOP" condition. Figure 25 shows an auto-increment read cycle terminated by a STOP or RESTART condition.
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Registers and Programming
CH7003B
The CH7003 is a fully programmable device, providing for full functional control through a set of registers accessed from the I2C port. The CH7003 contains a total of 31 registers, which are listed in Table 15 and described in detail under Register Descriptions. Detailed descriptions of operating modes and their effects are contained in the previous section, Functional Description. An addition (+) sign in the Bits column below signifies that the parameter contains more than 8 bits, and the remaining bits are located in another register.
Table 15. Register Map
Register
Display Mode Flicker Filter Video Bandwidth Input Data Format Clock Mode Start Active Video Position Overflow Black Level
Symbol
DMR FFR VBW IDF CM SAV PO BLR HPR
Address
00H 01H 03H 04H 06H 07H 08H 09H 0AH 0BH 0DH 0EH 10H 11H 13H 14H 15H 17H 18H - 1FH 20H 21H 22H - 24H 25H 26H - 29H 2AH 8 2 7 6 7 8+ 3 8 8+ 8+ 4 5 4 3 5 8+ 8+ 6
Bits
Functional Summary
Display mode selection Flicker filter mode selection Luma and chroma filter bandwidth selection Data format and bit-width selections Sets the clock mode to be used Active video delay setting MSB bits of position values Black level adjustment Input latch clock edge select Enables horizontal movement of displayed image on TV Enables vertical movement of displayed image on TV Determines the horizontal and vertical sync polarity Enables power saving modes Detection of TV presence Contrast enhancement setting Contains the MSB bits for the M and N PLL values Sets the PLL M value - bits (7:0) Sets the PLL N value - bits (7:0) Determines the clock output at pin 41 Determines the subcarrier frequency Controls for the PLL and memory sections Control of CIV value Readable register containing the calculated subcarrier increment value Device version number Reserved for test (details not included herein) Current register being addressed
Horizontal Position Vertical Position VPR SPR Sync Polarity Power Management Connection Detect Contrast Enhancement PLL M and N extra bits PLL-M Value PLL-N Value Buffered Clock Subcarrier Frequency Adjust PLL and Memory Control CIV Control Calculated Fsc Increment Value Version ID Test Address PMR CDR CE MNE PLLM PLLN BCO FSCI PLLC CIVC CIV VID TR AR
4 each 6 3 8 each 5 30 6
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Register Descriptions (continued)
Table 16. I2C Alternate Register Map
Register
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 2AH AR5 CIV23 CIV15 CIV7 CIV22 CIV14 CIV6 CIV21 CIV13 CIV5 CIV20 CIV12 CIV4 VID4 AR4 CIV19 CIV11 CIV3 VID3 AR3 PLLCPl PLLCAP \ \ SHF2 SHF1 SHF0 FSCI31 FSCI27 FSCI23 FSCI19 FSCI15 FSCI11 FSCI7 FSCI3 PLLS SCO2 FSCI30 FSCI26 FSCI22 FSCl18 FSCl14 FSCl10 FSCI6 FSCI2 PLL5VD ClVH1 CIV18 CIV10 CIV2 VID2 AR2 SCO1 M7 N7 M6 N6 M5 N5 Reserved M4 N4 Reserved M3 N3 N9 M2 N2 N8 M1 N1 YT CT CE2 CVBST CE1 SCART DES Reset* SYO PD2 VSP PD1 BL7 HP7 VP7 BL6 HP6 VP6 BL5 HP5 VP5 BL4 HP4 VP4 BL3 HP3 VP3 CFRB SAV7 M/S* SAV6 SAV5 MCP SAV4 XCM1 SAV3 XCM0 SAV2 SAV8 BL2 HP2 VP2 PCM1 SAV1 HP8 BL1 HP1 VP1 FLFF CVBW DACG CBW1 RGBBP CBW0 YPEAK IDF3 YSV1 IDF2 YSV0 IDF1
CH7003B
Bit 7
IR2
Bit 6
IR1
Bit 5
IRO
Bit 4
VOS1
Bit 3
VOS0
Bit 2
SR2
Bit 1
SR1 FF1
Bit 0
SR0 FF0 YCV IDF0 PCM0 SAV0 VP8 BL0 HP0 VP0 HSP PD0 SENSE CE0 M8 M0 N0 SCO0 FSCI28 FSCI24 FSCI20 FSCl16 FSCI12 FSCI8 FSCI4 FSCI0 MEM5V AClV CIV16 CIV8 CIVO VID0 AR0
FSCI29 FSCI25 FSCI21 FSCl17 FSCl13 FSCl9 FSCI5 FSCI1 PLL5VA ClVH0 CIV17 CIV9 CIV1 VID1 AR1
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Register Descriptions Display Mode Register
CH7003B
Symbol: DMR
Address: 00H Bits: 8
Bit: Symbol: Type: Default:
7
IR2 R/W 0
6
IR1 R/W 1
5
IR0 R/W 1
4
VOS1 R/W 0
3
VOS0 R/W 1
2
SR2 R/W 0
1
SR1 R/W 1
0
SR0 R/W 0
This register provides programmable control of the CH7003 display mode, including input resolution (IR[2:0]), output TV standard (VOS[1:0]), and scaling ratio (SR[2:0]). The mode of operation is determined according to the table below (default is Mode 17 640x480 input, NTSC output, 7/8's scaling).
Table 17. Mode Selection
Mode IR[2:0] VOS [1:0] SR [2:0] Input Data Format (Active Video)
512x384 512x384 512x384 512x384 720X400 720x400 720x400 720x400 640x400 640x400 640x400 640x400 640x400 640x480 640x480 640x480 640x480 640x480 640x480 800x600 800x600 800x600 800x600 800x600 800x600
Total Pixels/Line x Total Lines/Frame
840x500 840x625 800x420 784x525 1125X500 1116x625 945x420 936x525 1000x500 1008x625 840x420 840x525 840x600 840x500 840x625 840x750 784x525 784x600 800x630 944x625 960x750 936x836 1040x630 1040x700 1064x750
Output Format
Scaling
Pixel Clock (MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
000 000 000 000 001 001 001 001 010 010 010 010 010 011 011 011 011 011 011 100 100 100 100 100 100
00 00 01 01 00 00 01 01 00 00 01 01 01 00 00 00 01 01 01 00 00 00 01 01 01
000 001 000 001 000 001 000 001 000 001 000 001 010 000 001 011 001 010 011 001 011 100 011 100 101
PAL PAL NTSC NTSC PAL PAL NTSC NTSC PAL PAL NTSC NTSC NTSC PAL PAL PAL NTSC NTSC NTSC PAL PAL PAL NTSC NTSC NTSC
5/4 1/1 5/4 1/1 5/4 1/1 5/4 1/1 5/4 1/1 5/4 1/1 7/8 5/4 1/1 5/6 1/1 7/8 5/6 1/1 5/6 3/4 5/6 3/4 7/10
21.000000 26.250000 20.139860 24.671329 28.125000 34.875000 23.790210 29.454545 25.000000 31.500000 21.146853 26.433566 30.209790 21.000000 26.250000 31.500000 24.671329 28.195804 30.209790 29.500000 36.000000 39.000000 39.272727 43.636364 47.832168
VOS[1:0] Output Format
00 PAL
01 NTSC
10 PAL-M
11 NTSC-J
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Register Descriptions (continued) Flicker Filter Register
CH7003B
Symbol: FFR Address: 01H Bits: 2
6 5 4 3 2 1
FF1 R/W 0
Bit: Symbol: Type: Default:
7
0
FF0 R/W 1
The flicker filter register provides for adjusting the operation of the scan rate conversion/flicker filter. As a function of the CH7003 scaling/filtering architecture, the selection of scaling modes affects the available selections of flicker filtering. When operating in non-scaling modes (i.e., modes with scaling of 1/1), the FF[1:0] selects from four different amounts of flicker reduction. When operating in modes with scaling other than 1/1, FF[1] selects from two different amounts of flicker reduction, where bit FF[0] is ignored in these scaling settings. The tables below show the various flicker filter settings.
Table 18. Non-scaled Modes (1/1 ratio)
FFR[1:0]
00 01 10 11
Mode
0:1:0 1:2:1 1:3:1 1:1:1
Comments
No filtering (flicker filtering is disabled) Moderate flicker filtering (default mode) Low flicker reduction High flicker reduction
Table 19. Scaled Modes (non1/1scale ratio)
FFR[1:0]
0X 1X
Mode
3-line 4-line
Comments
3-line flicker filter, moderate flicker reduction 4-line flicker filter, minimum flicker
Video Bandwidth Register
Symbol: VBW Address: 03H Bits: 7
5
CBW1 R/W 0
Bit: Symbol: Type: Default:
7
FLFF R/W 0
6
CVBW R/W 0
4
CBW0 R/W 0
3
YPEAK R/W 0
2
YSV1 R/W 0
1
YSV0 R/W 0
0
YCV R/W 0
This register enables the selection of alternative filters for use in the luma and chroma channels. There are currently 4 filter options defined for the chroma channel, 4 filter options in the S-Video luma channel and two filter options in the composite luma channel. Table 20 and Table 21 show the various settings.
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Register Descriptions (continued)
Table 20. Luma Filter Bandwidth
YCV
0 1 YSV[1:0] 00 01 10 11 YPEAK 0 1
CH7003B
Luma Composite Video Filter Adjust
Low bandwidth High bandwidth Luma S-Video Filter Adjust Low bandwidth Medium bandwidth High bandwidth Reserved (decode this and handle the same as 10) Disables the Y-peaking circuit Disables the peaking filter in luma S-Video channel Enables the peaking filter in luma S-Video channel
Table 21. Chroma Filter Bandwidth
CBW[1:0]
00 01 10 11
Chroma Filter Adjust
Low bandwidth Medium bandwidth Med-high bandwidth High bandwidth
*
Bit 6 (CVBW) outputs the S-Video luma signal on both the S-Video luma output and the CVBS output. A "1" in this location enables the output of a black and white image on composite, thereby eliminating the degrading effects of the color signal (such as dot crawl or false colors), which is useful for viewing text with high accuracy. Bit 7 (FLFF) controls the flicker filter used in the 7/10's scaling modes. In these scaling modes, setting FLFF to one causes a five line flicker filter to be used. The default setting of zero uses a four line flicker filter.
*
Input Data Format Register
Symbol: IDF Address: 04H Bits: 6
5
RGBBP R/W 0
Bit: Symbol: Type: Default:
7
6
DACG R/W 0
4
3
IDF3 R/W 0
2
IDF2 R/W 0
1
IDF1 R/W 0
0
IDF0 R/W 0
This register sets the variables required to define the incoming pixel data stream, including data format and input bit width, and VBI encoding.
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Register Descriptions (continued)
Table 22. Input Data Format
IDF[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001-1111
Description
16-bit non-multiplexed RGB (16-bit color, 565) input 16-bit non-multiplexed YCrCb (24-bit color) input (Y non-multiplexed, CrCb multiplexed) 16-bit multiplexed RGB (24-bit color) input 15-bit non-multiplexed RGB (15-bit color, 555) input 12-bit multiplexed RGB (24-bit color) input ("C" multiplex scheme) 12-bit multiplexed RGB2 (24-bit color) input ("I" multiplex scheme) 8-bit multiplexed RGB (24-bit color, 888) input 8-bit multiplexed RGB (16-bit color, 565) input 8-bit multiplexed RGB (15-bit color, 555) input 8-bit multiplexed YCrCb (24-bit color) input (Y, Cr and Cb are multiplexed)
RGBBP (bit 5): Setting this bit enables the RGB pass-through mode. Setting this bit to a 1 causes the input RGB signal to be directly output at the DACs (subject to a pipeline delay). If RGBBP=0, the bypass mode is disabled. DACG (bit 6): This bit controls the gain of the D/A converters. When DACG=0, the nominal DAC current is 71 A, which provides the correct levels for NTSC and PAL-M. When DACG=1, the nominal DAC current is 76A, which provides the correct levels for PAL and NTSC-J.
Clock Mode Register
Symbol: CM Address: 06H Bits: 7
6
M/S* R/W 0
Bit: Symbol: Type: Default:
7
CFRB R/W 0
5
4
MCP R/W 1
3
XCM1 R/W 0
2
XCM0 R/W 0
1
PCM1 R/W 0
0
PCM0 R/W 0
The setting of the clock mode bits determines the clocking mechanism used in the CH7003. The clock modes are shown in the table below. PCM controls the frequency of the pixel clock, and XCM identifies the frequency of the XCLK input clock.
Note: For what was formerly defined as the master mode, the user must now externally connect the P-OUT clock to the XCLK input pin. Although it is possible to set the XCM [1:0] and PCM[1:0] values independent of the input data format, there are only certain combinations of input data format, XCM and PCM, that will result in valid data being demultiplexed at the input of the device. Refer to the "Input Data Format Register" for these combinations.
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Register Descriptions (continued)
Table 23. Clock Modes
XCM[1:0]
00 00 00 01 01 01 1X 1X 1X
CH7003B
PCM[1:0]
00 01 1X 00 01 1X 00 01 1X
XCLK
1X 1X 1X 2X 2X 2X 3X 3X 3X
P-OUT
1X 2X 3X 1X 2X 3X 1X 2X 3X
Input Data Modes Supported
0, 1, 2, 3, 4, 5, 7, 8, 9 0, 1, 2, 3, 4, 5, 7, 8, 9 0, 1, 2, 3, 4, 5, 7, 8, 9 2, 4, 5, 7, 8, 9 2, 4, 5, 7, 8, 9 2, 4, 5, 7, 8, 9 6 6 6
The Clock Mode Register also contains the following bits: * * * MCP (bit 4) determines which edge of the pixel clock output will be used to latch input data. Zero selects the negative edge, one selects the positive edge. Bit 5 Unused M/S* (bit 6) determines whether the device operates in master or slave clock mode. In master mode (1), the 14.31818MHz clock is used as a frequency reference, and the display mode register is decoded to determine the PLL divider settings. In slave mode (0) the XCLK input is used as a reference to the PLL, and is divided by the value specified by XCM[1:0]. The divide by N is forced to one. Bit 7 (CFRB) sets whether the chroma subcarrier free-runs, or is locked to the video signal. One causes the subcarrier to lock to the TV vertical rate, and should be used when the ACIV bit is set to zero. Zero causes the subcarrier to free-run, and should be used when the ACIV bit is set to one.
*
Start Active Video Register
Symbol: SAV Address: 07H Bits: 8
5
SAV5 R/W 0
Bit: Symbol: Type: Default:
7
SAV7 R/W 0
6
SAV6 R/W 0
4
SAV4 R/W 0
3
SAV3 R/W 0
2
SAV2 R/W 0
1
SAV1 R/W 0
0
SAV0 R/W 0
This register sets the delay, in pixel increments, from leading edge of horizontal sync to start of active video. The entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus the MSB value contained in the position overflow register, bit SAV8. This is decoded as a whole number of pixels, which can be set anywhere between 0 and active data must be a multiple of two clocks. In any 3X clock mode, the number of 3X clocks from the leading edge of sync to the first active data must be a multiple of three clocks.
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Register Descriptions (continued) Position Overflow Register
CH7003B
Symbol: PO Address: 08H Bits: 3
5 4 3 2
SAV8 R/W 0
Bit: Symbol: Type: Default:
7
6
1
HP8 R/W 0
0
VP8 R/W 0
This position overflow register contains the MSB values for the SAV, HP, and VP values, as follows: * * * VP8 (bit 0) is the MSB of the vertical position value (see explanation under "Vertical Position Register"). HP8 (bit 1) is the MSB of the horizontal position value (see explanation under "Horizontal Position Register"). SAV8 (bit 2) is the MSB of the start of active video value (see explanation under "Start Active Video Register").
Black Level Register
Symbol: BLR Address: 09H Bits: 8
6
BL6 R/W 1
Bit: Symbol: Type: Default:
7
BL7 R/W 0
5
BL5 R/W 1
4
BL4 R/W 1
3
BL3 R/W 1
2
BL2 R/W 1
1
BL1 R/W 1
0
BL0 R/W 1
This register sets the black level. The luminance data is added to this black level, which must be set between 90 and 208, with the default value being 127. Recommended values for NTSC and PAL-M are 127, 105 for PAL and 100 for NTSC-J. This value must be set to zero when in SCART mode.
Horizontal Position Register
Symbol: HPR Address: 0AH Bits: 8
5
HP5 R/W 0
Bit: Symbol: Type: Default:
7
HP7 R/W 0
6
HP6 R/W 0
4
HP4 R/W 1
3
HP3 R/W 0
2
HP2 R/W 0
1
HP1 R/W 0
0
HP0 R/W 0
The horizontal position register is used to shift the displayed TV image in a horizontal direction (left or right) to achieve a horizontally centered image on screen. The entire bit field, HP[8:0] is comprised of this register HP[7:0] plus the MSB value contained in the position overflow register, bit HP8. Increasing this value moves the displayed image position RIGHT; decreasing this value moves the displayed image position LEFT. Each increment moves the image position by 4 input pixels.
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Register Descriptions (continued) Vertical Postiion Register
CH7003B
Symbol: VPR Address: 0BH Bits: 8
5
VP5 R/W 0
Bit: Symbol: Type: Default:
7
VP7 R/W 0
6
VP6 R/W 0
4
VP4 R/W 0
3
VP3 R/W 0
2
VP2 R/W 0
1
VP1 R/W 0
0
VP0 R/W 0
This register is used to shift the displayed TV image in a vertical direction (up or down) to achieve a vertically centered image on screen. This bit field, VP[8:0] represents the TV line number (relative to the VGA vertical sync) used to initiate the generation and insertion of the TV vertical interval (i.e., the first sequence of equalizing pulses). Increasing values delay the output of the TV vertical sync, causing the image position to move UP on the TV screen. Decreasing values, therefore, move the image position DOWN. Each increment moves the image position by one TV line (approximately 2 VGA lines). The maximum value that should be programmed into the VP[8:0] value is the number of TV lines minus 1, divided by 2 (262, 312 or 313). When panning the image up, the number should be increased until (TVLPF-1) / 2 is reached; the next step should be to reset the value to zero. When panning the image down the screen, the VP[8:0] value should be decremented until the value zero is reached. The next step should set the value to (TVLPF-1) / 2, and then decrementing can continue. If this value is programmed to a number greater than (TV lines per frame-1) /2, a TV vertical SYNC will not be generated.
Sync Polarity Register
Symbol: SPR Address: 0DH Bits: 4
6 5 4 3
DES R/W 0
Bit: Symbol: Type: Default:
7
2
SYO R/W 0
1
VSP R/W 0
0
HSP R/W 0
This register provides selection of the synchronization signal input to, or output from, the CH7003. * HSP (bit 0) is Horizontal Sync Polarity - an HSP value of zero means the horizontal sync is active low, and a value of one means the horizontal sync is active high. * * * VSP (bit 1) is Vertical Sync Polarity - a VSP value of zero means the vertical sync is active low, and a value of one means the vertical sync is active high. SYO (bit 2) is Sync Direction - a SYO value of zero means that H and V sync are input to the CH7003. A value of one means that H and V sync are output from the CH7003. DES (bit 3) is Detect Embedded Sync - a DES value of zero means that H and V sync will be obtained from the direct pin inputs. A DES value of one means that H and V sync will be detected from the embedded codes on the pixel input stream. Note that this will only be valid for the YCrCb input modes.
Note: When sync direction is set to be an output, horizontal sync will use a fixed pulse width of 64 pixels and vertical sync will use a fixed pulse width of 2 lines.
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Register Descriptions (continued) Power Management Register
CH7003B
Symbol: PMR Address: 0EH Bits: 5
5 4
SCART R/W 0
Bit: Symbol: Type: Default:
7
6
3
Reset* R/W 1
2
PD2 R/W 0
1
PD1 R/W 1
0
PD0 R/W 1
This register provides control of the power management functions, a software reset (ResetB), and the SCART output enable. The CH7003 provides programmable control of its operating states, as described in the table below.
Table 24. Power Management
PD[2:0]
000 001
Operating State
Composite Off Power Down
Functional Description
CVBS DAC is powered down. Most pins and circuitry are disabled (except for the bandgap reference and the buffered clock outputs which are limited to the 14MHz output and VCO divided outputs). S-Video DACs are powered down. All circuits and pins are active. All circuitry is powered down, except I 2C circuit
010 011 1XX
S-Video Off Normal (On) Full Power Down
Reset* (bit 3) is soft reset. Setting this bit to 0 will reset all circuitry requiring a power on reset, except for this bit itself and the I2C state machines. After reset, this bit should be set back to 1 for normal operation to continue. SCART (bit 4) is the SCART enable. Setting SCART = 0 means the CH7003 will operate normally, outputting Y/C and CVBS from the three DACs. SCART=1 enables SCART output, which will cause R, G and B to be output from the DACs and composite sync from the CSYNC pin.
Note: For complete details regarding the operation of these modes, see the Power Management in Functional Description sections.
Connection Detect Register
Symbol: CDR Address: 10H Bits: 4
5 4 3
YT R 0
Bit: Symbol: Type: Default:
7
6
2
CT R 0
1
CVBST R 0
0
SENSE W 0
The Connection Detect Register provides a means to sense the connection of a TV to either S-Video or Composite video outputs. The status bits, YT, CT, and CVBST correspond to the DAC outputs for S-Video (Y and C outputs) and Composite video (CVBS), respectively. However, the values contained in these status bits are NOT VALID until a sensing procedure is performed. Use of this register requires a sequence of events to enable the sensing of outputs, then reading out the applicable status bits. The detection sequence works as follows:
1. Ensure the power management register Bits 2-0 is set to 011 (normal mode).
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Register Descriptions (continued)
CH7003B
2. Set the SENSE bit to a 1. This forces a constant current output onto the Y, C, and CVBS outputs. Note that during SENSE = 1, these 3 analog outputs are at steady state and no TV synchronization pulses are asserted. 3. Reset the SENSE bit to 0. This triggers a comparison between the voltage sensed on these analog outputs and the reference value expected (Vthreshold = 1.235V). If the measured voltage is below this threshold value, it is considered connected, if it is above this voltage it is considered unconnected. During this step, each of the three status bits corresponding to individual analog outputs will be set if they are NOT connected. 4. Read the status bits. The status bits, YT, CT, and CVBST (corresponding to S-Video Y and C outputs and composite video) now contain valid information which can be read to determine which outputs are connected to a TV. Again, a "0" indicates a valid connection, a "1" indicates an unconnected output.
Contrast Enhancement Register
Symbol: CE Address: 11H Bits: 3
5 4 3 2
CE2 R/W 0
Bit: Symbol: Type: Default:
7
6
1
CE1 R/W 1
0
CE0 R/W 1
This register provides control of the contrast enhancement feature of the CH7003, according to the table below. At a setting of 000, the video signal will be pulled towards the maximum black level. As the value of CE[2:0] is increased, the amount that the signal is pulled towards black is decreased until unity gain is reached at a setting of 011. From this point on, the video signal is pulled towards the white direction, with the effect increasing with increasing settings of CE[2:0].
Table 25. Contrast Enhancement Function
CE[2:0]
000 001 010 011 100 101 110 111
Description (all gains limited to 0-255)
Contrast enhancement gain 3 Yout = (5/4)*(Yin-102) = Enhances Black Contrast enhancement gain 2 Yout = (9/8)*(Yin-57) Contrast enhancement gain 1 Yout = (17/16)*(Yin-30) Normal mode Yout = (1/1)*(Yin-0) = Normal Contrast Contrast enhancement gain 1 Yout = (17/16)*(Yin-0) Contrast enhancement gain 2 Yout = (9/8)*(Yin-0) Contrast enhancement gain 3 Yout = (5/4)*(Yin-0) Contrast enhancement gain 4 Yout = (3/2)*(Yin-0) = Enhances White
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Register Descriptions (continued)
CH7003B
256 224 192 160 128 96 64 32 0 0 32 64 96 128 160 192 224 256
Figure 26: Luma Transfer Function at different contrast enhancement settings
PLL Overflow Register
Symbol: MNE Address: 13H Bits: 5
5 4
Reserved R/W 0
Bit: Symbol: Type: Default:
7
6
3
Reserved R/W 0
2
N9 R/W 0
1
N8 R/W 0
0
M8 R/W 0
The PLL Overflow Register contains the MSB bits for the `M' and `N' values, which will be described in the PLLM and PLL-N registers, respectively. The reserved bits should not be written to.
PLL M Value Register
Symbol: PLLM Address: 14H Bits: 8
6
M6 R/W 1
Bit: Symbol: Type: Default:
7
M7 R/W 0
5
M5 R/W 0
4
M4 R/W 0
3
M3 R/W 0
2
M2 R/W 0
1
M1 R/W 0
0
M0 R/W 1
The PLL M value register determines the division factor applied to the frequency reference clock before it is input to the PLL phase detector when the CH7003 is operating in master or pseudo-master clock mode. In slave mode, an external pixel clock is used instead of the frequency reference, and the division factor is determined by the XCM[3:0] value. This register contains the lower 8 bits of the complete 9-bit M value.
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Register Descriptions (continued) PLL N Value Register
CH7003B
Symbol: PLLN Address: 15H Bits: 8
6
N6 R/W 0
Bit: Symbol: Type: Default:
7
N7 R/W 1
5
N5 R/W 0
4
N4 R/W 0
3
N3 R/W 0
2
N2 R/W 0
1
N1 R/W 0
0
N0 R/W 0
The PLL N value register determines the division factor applied to the VCO output before being applied to the PLL phase detector, when the CH7003 is operating in master or pseudo-master mode. In slave mode, the value of `N' is always 1. This register contains the lower 8 bits of the complete 10-bit N value. The pixel clock generated in a master and pseudo-master modes is calculated according to the equation below: Fpixel = Fref* [(N+2) / (M+2)] When using a 14.318 MHz frequency reference, the required M and N values for each mode are shown in the table below.
Table 26. M and N Values for Each Mode
Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 VGA Resolution, TV Standard, Scaling Ratio 512X384, PAL, 5:4 512X384, PAL, 1:1 512X384, NTSC, 5:4 512X384, NTSC, 1:1 720X400, PAL, 5:4 720X400, PAL, 1:1 720X400, NTSC, 5:4 720X400, NTSC, 1:1 640X400, PAL, 5:4 640X400, PAL, 1:1 640X400, NTSC, 5:4 640X400, NTSC, 1:1 640X400, NTSC, 7:8 N 10bits 20 9 126 110 53 339 106 70 108 9 94 22 190 M 9bits 13 4 89 63 26 138 63 33 61 3 63 11 89 Mode 13 14 15 16 17 18 19 20 21 22 23 24 VGA Resolution, TV Standard, Scaling Ratio 640X480, PAL, 5:4 640X480, PAL, 1:1 640X480, PAL, 5:6 640X480, NTSC, 1:1 640X480, NTSC, 7:8 640X480, NTSC, 5:6 800X600, PAL, 1:1 800X600, PAL, 5:6 800X600, PAL, 3:4 800X600, NTSC, 5:6 800X600, NTSC, 3:4 800X600, NTSC, 7:10 N 10bits 20 9 9 110 126 190 647 86 284 94 62 302 M 9-bits 13 4 3 63 63 89 313 33 103 33 19 89
Buffered Clock Output Register
Symbol: BCO Address: 17H Bits: 5
5
SHF2 R/W 0
Bit: Symbol: Type: Default:
7
6
4
SHF1 R/W 0
3
SHF0 R/W 0
2
SCO2 R/W 0
1
SCO1 R/W 0
0
SCO0 R/W 0
The buffered clock output register determines which clock is selected to be output at the buffered clock output pin, and what frequency value should be output if a VCO derived signal is output. The tables below show the possible output signals.
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Register Descriptions (continued)
Table 27. Clock Output Selection
SCO[2:0]
000 001 010 011 100 101 110 111 14 MHz crystal (For test use only) VCO divided by K3 (see Table 28 ) Field ID signal (for test use only) (for test use only) TV horizontal sync (for test use only) TV vertical sync (for test use only)
CH7003B
Buffered Clock Output
Table 28. K3 Selection
SHF[2:0]
000 001 010 011 100 101 110 111
K3
2.5 3 3.5 4 4.5 5 6 7
Sub-carrier Value Registers
Symbol: FSCI Address: 018H - 1FH Bits: 4 each
5 4 3
FSCI# R/W
Bit: Symbol: Type: Default:
7
6
2
FSCI# R/W
1
FSCI# R/W
0
FSCI# R/W
The lower four bits of registers18H through 1F contain a 32-bit value which is used as an increment value for the ROM address generation circuitry. the bit locations fare shown below: Register 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Contents FSCI[31:28] FSCI[27:24] FSCI[23:20] FSCI[19:16] FSCI[15:12] FSCI[11:8] FSCI[7:4] FSCI[3:0]
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Register Descriptions (continued)
CH7003B
When the CH7003 is operating in the master clock mode, the tables below should be used to set the FSCI registers. When using these values, the ACIV bit in register 21H should be set to "0" and the CFRB bit in register 06H should be set to"1".
Table 29. FSCI Values (525-Lines Modes)
Mode
2 3 6 7 10 11 12 16 17 18 22 23 24
NTSC "Normal Dot Crawl"
763,363,328 623,153,737 574,429,782 463,962,517 646,233,505 516,986,804 452,363,454 623,153,737 545,259,520 508,908,885 521,957,831 469,762,048 428,554,851
NTSC "No Dot Crawl"
763,366,524 623,156,346 574,432,187 463,964,459 646,236,211 516,988,968 452,365,347 623,156,346 545,261,803 508,911,016 521,960,016 469,764,015 438,556,645
PAL-M "Normal Dot Crawl
762,524,467 622,468,953 573,798,541 463,452,668 645,523,358 516,418,687 451,866,351 622,468,953 544,660,334 508,349,645 521,384,251 469,245,826 428,083,911
Table 30. FSCI Values (625-Lines Modes)
Mode
0 1 4 5 8 9 13 14 15 19 20 21
PAL "Normal Dot Crawl"
806,021,060 644,816,848 601,829,058 485,346,014 677,057,690 537,347,373 806,021,060 644,816,848 537,347,373 645,499,916 528,951,320 488,262,757*
PAL-N "Normal Dot Crawl"
651,209,077 520,967,262 486,236,111 392,125,896 547,015,625 434,139,385 651,209,077 520,967,262 434,139,385 521,519,134 427,355,957 394,482,422
When the CH7003 is operating in the slave clock mode, the ACIV bit in register 21H should be set to "1" and the CFRB bit in register 06H should be set to "0". *Note: For reduced cross-color and cross-luminance artifacts, a value of 488,265,597 can be used with CFRB = "0" & ACIV = "0".
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Register Descriptions (continued) PLL Control Register
CH7003B
Symbol: PLLC Address: 20H Bits: 6
6 5
PLLCPI R/W 0
Bit: Symbol: Type: Default:
7
4
PLLCAP R/W 0
3
PLLS R/W 1
2
PLL5VD R/W 0
1
PLL5VA R/W 1
0
MEM5V R/W 0
The following PLL and memory controls are available through the PLL control register: MEM5V PLL5VA PLL5VD PLLS MEM5V is set to 1 when the memory supply is 5 volts. The default value of 0 is used when the memory supply is 3.3 volts. PLL5VA is set to 1 when the phase-locked loop analog supply is 5 volts (default). A value of 0 is used when the phase-locked loop analog supply is 3.3 volts. PLL5VD is set to 1 when the phase-locked loop digital supply is 5 volts. A value of 0 is used when the phase-locked loop digital supply is 3.3 volts (default). PLLS controls the number of stages used in the PLL. When the PLL5VA is 1 (5V analog PLL supply) PLLS should be 1, and seven stages are used. When PLL5VA is 0 (3.3V analog PLL supply) PLLS shold be 0, and five stages are used. PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs. Mode is shown in Table 30. PLLCHI controls the charge pump current of the PLL. The default value of 0 should be used.
PLLCAP PLLCPI
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Register Descriptions (continued)
Table 31. PLL Capacitor Setting
Mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
CH7003B
PLLCAP Value
1 1 1 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 1 0 1 1 0
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Register Descriptions (continued) CIV Control Register
CH7003B
Symbol: CIVC Address: 21H Bits: 3
6 5 4 3 2
CIVH1 R/W 0
Bit: Symbol: Type: Default:
7
1
CIVH0 R/W 0
0
ACIV R/W 1
The following controls are available through the CIV control register: ACIV 1, the subcarrier generation must be forced to free-run mode. CIVH[1:0] These bits control the hysteresis circuit which is used to calculate the CIV value. When the automatic calculated increment value is 1, the number calculated and present at the CIV registers will automatically be used as the increment value for subcarrier generation, removing the need for the user to read the CIV value and write in a new FSCI value. Whenever this bit is set to
Calculated Increment Value Register
Symbol: CIV Address: 22H - 24H Bits: 8 each
4
CIV# R 0
Bit: Symbol: Type: Default:
7
CIV# R 0
6
CIV# R 0
5
CIV# R 0
3
CIV# R 0
2
CIV# R 0
1
CIV# R 0
0
CIV# R 0
The CIV registers 22H through 24H, toghether with 2 bits from register 2H, define a 24-bit value, which is the calculated increment value that should be used as the upper 24 bits of FSCI. This value is determined by a comparison of the pixel clock and the 14MHz clock. The bit locations and calculation of CIV are specified as the following: Register 22H 23H 24H Contents CIV[23:16] CIV[15:8] CIV[7:0]
Version ID Register
Symbol: VID Address: 25H Bits: 5
6
N/A R 0
Bit: Symbol: Type: Default:
7
N/A R 0
5
N/A R 0
4
VID4 R 0
3
VID3 R 0
2
VID2 R 0
1
VID1 R 1
0
VID0 R 0
This read-only register contains a 5-bit value indicating the identification number assigned to this version of the CH7003. The default value shown is pre-programmed into this chip and is useful for checking for the correct version of this chip, before proceeding with its programming.
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Register Descriptions (continued) Address Register
CH7003B
Symbol: AR Address: 2AH Bits: 6
6 5
AR5 R/W X
Bit: Symbol: Type: Default:
7
4
AR4 R/W X
3
AR3 R/W X
2
AR2 R/W X
1
AR1 R/W X
0
AR0 R/W X
The Address Register points to the register currently being accessed. Since the most significant four bits of all addresses are zero, this register contains only the six least significant bits, AR[5:0].
Electrical Specification
Table 32. Absolute Maximum Ratings
Symbol Description
VDD relative to GND Input voltage of all digital pins1
Min - 0.5 GND - 0.5
Typ
Max 7.0 VDD + 0.5
Units V V Sec C C C C
TSC TAMB TSTOR TJ TVPS
Analog output short circuit duration Ambient operating temperature Storage temperature Junction temperature Vapor phase soldering (one minute)
Indefinite - 55 - 65 85 150 150 220
Notes: 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated under the normal operating conditions section of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 The device is fabricated using high-performance CMOS technology. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5V can induce destructive latchup.
Table 33. Recommended Operating Conditions
Symbol VDD AVDD DVDD TA RL Description
DAC power supply voltage Analog supply voltage Digital supply voltage Ambient operating temperature Output load to DAC outputs
Min
4.75 4.75 3.0 0
Typ
5.00 5.00 3.3 25 37.5
Max
5.25 5.25 3.6 70
Units
V V V C
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Electrical Specifications (continued)
CH7003B
Table 34. Electrical Characteristics (Operating Conditions: TA = 0oC - 70oC, VDD = 5V 5%)
Symbol Description
Video D/A resolution Full scale output current Video level error
Min
9
Typ
9 36.4
Max
9 10
Unit
Bits mA %
Note: As applied to Tables 30, 31,32, 33, 34. Recommended Operating Conditions are used as test conditions unless otherwise specified. External voltage reference used with RSET = 360 , VREF = 1.235V, and NTSC CCIR601 operation. Typical values are based on 25o C and typical supply levels.
Table 35. CH7003 Supply Current Characteristics
Description
Normal Operation IDD1 IDD2 IDD3 DVDD supply current AVDDsupply current VDD supply current Normal Operation S-Video only IDD1 IDD2 IDD3 DVDD supply current AVDDsupply current VDD supply current Normal Operation, composite only IDD1 IDD2 IDD3 Partial Power Down IDD1 IDD2 IDD3 Full Power Down IDD1 IDD2 IDD3 DVDD supply current AVDDsupply current VDD supply current <0.1 <0.2 0.2 mA mA mA DVDD supply current AVDDsupply current VDD supply current 9 9 0.2 mA mA mA DVDD supply current AVDDsupply current VDD supply current 57 9 42 mA mA mA 57 9 65 mA mA mA 57 9 102 mA mA mA
Min
Typ
Max
Units
Notes: 5. The above data is typical at 25oC with the following supply voltages: DVDD=3.6V, AVDD=5.0V and VDD=5.0V 6. Current is mesured in normal circuit configuration with output loads connected; device operating in mode 17 with P-OUT at 2X. 7. Actual current will depend on many factors, including operating mode, image content, output clock selections, etc. This table is intended as a general guide only.
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Electrical Specifications (continued)
Table 36. Digital Inputs/Outputs
Symbol
VSDOL VIICIH VIICIL VDATAIH VDATAIL VP-OUTOH VP-OUTOL
CH7003B
Description
SD Output Low Voltage SD Input High Voltage SD Input Low Voltage D[0-15] Input High Voltage D[0-15] Input Low Voltage P-OUT Output High Voltage P-OUT Output Low Voltage
Test Condition
IOL = 3.2 mA
Min
Typ
Max
0.4
Unit
V V V V V V
3.4 GND-0.5 2.5 GND-0.5 IOL = - 400 A IOL = 3.2 mA 2.8
VDD + 0.5 1.4 DVDD+0.5 0.8
0.2
V
Note:
1. VIIC - refers to I2C pins SD and SC. 2. VDATA - refers to all digital pixel and clock inputs. 3. VSD - refers to I2C pin SD as an output 4. VP-OUT - refers to pixel data output.
Table 37. Timing - TV Encoder
Symbol
tP1 tPH1 tdc1 tP2 tPH2 tdc2 tP3 tPH3 tdc3
Description
Pixel Clock Period Pixel Clock High Time Pixel Clock Duty Cycle (tPH1/tP1) Pixel Clock Period Pixel Clock High Time Pixel Clock Duty Cycle (tPH2/tP2) Pixel Clock Period Pixel Clock High Time Pixel Clock Duty Cycle (tPH3/tP3) 40 40 10 20 8 40 10
Min
Typ
50 25 50 60 25 50 60 17 50 60
Max
Unit
nS nS % nS nS % nS nS %
Table 38. Timing - Graphics
Symbol
tHSW
t HD
Description
Horizontal Sync Pulse Width Pixel Clock to Horizontal Leading Edge Delay Setup time from Pixel Data to Pixel Clock Hold time from Pixel Clock to Pixel Data 1 2 2 2
Min
Typ
Max
17
Unit
tp nS nS nS
tSP1,tSP2,tSP3 tHP1,tHP2,tHP3
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CH7003B
ORDERING INFORMATION
Part number CH7003B-V CH7003B-T Package type PLCC TQFP Number of pins 44 44 Voltage supply 3V/5V 3V/5V
Chrontel
2210 O'Toole Avenue San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com
(c)1998 Chrontel, Inc. All Rights Reserved. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no liability for errors contained in this document. Printed in the U.S.A.
201-0000-023 Rev 4.1, 8/2/99
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Price & Availability of CH7003B

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